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High Speed Synchronous Power MOSFET Driver
POWER MANAGEMENT Description
The SC1205 is a cost effective Dual MOSFET Driver designed for switching High and Low side Power MOSFETs. Each driver is capable of driving a 3000pF load in 20ns max rise/fall time and has a 20ns max propagation delay from input transition to the gate of the power FET's. An internal Overlap Protection circuit prevents shootthrough from Vin to GND in the main and synchronous MOSFET's. The Adaptive Overlap Protection circuit ensures the Bottom FET does not turn on until the Top FET source has reached a voltage low enough to prevent cross-conduction. The high current drive capability (3A peak) allows fast switching, thus reducing switching losses at high (up to 1MHz) frequencies without overheating the driver. The high voltage CMOS process allows operation from 5-25 Volts at top MOSFET drain, thus making SC1205 suitable for battery powered applications. Connecting Enable pin (EN) to logic low shuts down both drives and reduces operating current to less than 10uA. An Under-Voltage-Lock-Out circuit is included to guarantee that both driver outputs are low when the 5V logic level is less than or equal to 4.4V (typ) at supply ramp up (4.35V at supply ramp down). An Internal temperature sensor shuts down all drives in the event of overtemperature. SC1205 is fabricated utilizing Bi-CMOS technology for low quiescent current. The SC1205 is offered in a standard SO-8 package.
SC1205
Features
Fast rise and fall times (15ns typical with 3000pf load) 3 Amp peak drive current 14ns max Propagation delay (BG going low) Adaptive Non-overlapping Gate Drives provide shoot-through protection Floating top drive switches up to 25V Under-Voltage lock-out Overtemperature protection Less than 10A supply current when EN is low Low cost
Applications
High Density sunchronous power supplies Motor Drives/Class-D amps/Half bridge drivers High frequency (to 1.2 MHz) operation allows use of small inductors and low cost caps in place of electrolytics High efficiency portable computers Battery powered applications
Typical Application Circuit
Vin 5-12V
2200uf 2.5m 10u,CER 10nf 10 70N03 TG DRN 70N03 EN CO SC1205 GND BG
To Processor VID control
1 2 3 4 5 6 7
VID4 VID3 VID2 VID1 VID0 ERROUT FB RREF
VCC BGOUT OC+ OUT1 OUT2 OCUVLO GND
16 15 14 13 12 11 10 9
+5V
VS
BST
BST
70N03 TG DRN 70N03
Rf
8
VS EN
SC2422A
CO SC1205
Ri
GND
Rref
BG
Vcore, 1.7v,40A
Revision: September 22, 2004
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SC1205
POWER MANAGEMENT Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied.
Parameter VCC Supply Voltage BST to PGND BST to DRN DRN to PGND DRN to PGND Pulse OVP_S to PGND Input Pin Continuous Power Dissipation Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering) 10 Sec.
Symbol VIMAXSW VMAXBST-PGND VMAXBST-DRN VMAXDRN-PGN VMAXPULSE VMAXOVP S-PGND CO Pd J C J A TJ TSTG TLEAD
Conditions
Maximum 7 30 7 -2 to 25
Units V V V V V V V W C/W C/W C C C
tPULSE < 100ns
-5 to 25 10 -0.3 to 7.3
Tamb = 25C, TJ = 125C Tcase = 25C, TJ =125C
0.66 2.56 40 150 0 to +125 -65 to +150 300
NOTE: (1) Specification refers to application circuit in Figure 1.
Electrical Characteristics
Unless specified: -0 < J < 125C; VCC = 5V; 4V < VBST < 26V
Parameter Pow er Supply Supply Voltage Quiescent Current, Operating Quiescent Current Under Voltage Lockout Start Threshold Hysteresis Logic Active Threshold EN High Level Input Voltage Low Level Input Voltage
Symbol
Conditions
Min
Typ
Max
Units
VCC Iq_op Iq_stby
V CC VCC = 5V, CO = OV EN = OV
4.15
5 1
6.0
V mA
10
A
VSTART VhysUVLO V AC T
4.2
4.4 0.05
4.6
V V
1.5
V
VIH VIL
2.0 0.8
V V
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SC1205
POWER MANAGEMENT Electrical Characteristics (Cont.)
Parameter CO High Level Input Voltage Low Level Input Voltage Thermal Shutdow n Over Temperature Trip Point Hysteresis High Side Driver Peak Output Current Output Resistance IPKH RsrcTG RsinkTG Low -Side Driver Peak Output Current Output Resistance IPKL RsrcBG RsinkBG duty cycle < 2%, tpw < 100 s, TJ = 125oC, VV S = 4.6V, VBG = 4V (src), or VLOWDR = 0.5V (sink) 3 1.2 1.0 A duty cycle < 2%, tpw < 100 s, TJ = 125C, VBST - VDRN = 4.5V, VTG = 4.0V (src) +VDRN or VTG = 0.05V (sink) +VDRN 3 1 .7 A TOTP THYST 165 10 C C VIH VIL 2.0 0.8 V V Symbol Conditions Min Typ Max Units
AC Operating Specifications
Parameter High Side Driver Rise Time Fall Time Propagation Delay Time, TG Going High Propagation Delay Time, TG Going Low Low -Side Driver Rise Time trBG CI = 3nF, V V S = 4.6V, TJ + 125C 15 24 ns trTG1 tfTG tpdhTG tpdlTG CI = 3nF, VBST - VDRN = 4.6V, TJ + 125C CI = 3nF, VBST - VDRN = 4.6V, TJ + 125C CI = 3nF, VBST - VDRN = 4.6V, TJ + 125C CI = 3nF, VBST - VDRN = 4.6V, TJ + 125C 14 12 20 15 23 19 32 24 ns ns ns ns Symbol Conditions Min Typ Max Units
Note: (1) This device is ESD sensitive. Use of standard ESD handling precautions is required.
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SC1205
POWER MANAGEMENT AC Operating Specifications (Cont.)
Parameter Low -Side Driver Fall Time Propagation Delay Time BG Going High Propagation Delay Time BG Going Low Under-Voltage Lockout V_5 ramping up V_5 ramping down tpdhUVLO tpdLUVLO EN is High EN is High 10 10 s s trBG tpdhBGHI tpdlBGHI CI = 3nF, V V S = 4.6V, TJ + 125C CI = 3nF, V V S = 4.6V, TJ + 125C CI = 3nF, V V S = 4.6V, TJ + 125C 13 12 7 21 19 12 ns ns ns Symbol Conditions Min Typ Max Units
Timing Diagrams
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SC1205
POWER MANAGEMENT Pin Configuration
Top View
Ordering Information
Device
(1)
P ackag e SO-8
Temp Range (TJ) 0 to 125C
SC1205CS.TR SC1205CSTRT(2)
(SO-8)
Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) Lead free product. This product is fully WEEE and RoHS compliant.
Pin Descriptions
Pin # 1 2 3 4 5 6 7 8 Pin Name DRN TG BST CO EN VS BG PGND Pin Function This pin connects to the junction of the switching and synchronous MOSFET's. This pin can be subjected to a -2V minimum relative to PGND without affecting operation. Output gate drive for the switching (high-side) MOSFET. Bootstrap pin. A capacitor is connected between BST and DRN pins to develop the floating bootstrap voltage for the high-side MOSFET. The capacitor value is typically between 0.1F and 1F (ceramic). TTL-level input signal to the MOSFET drivers. When high, this pin enables the internal circuitry of the device. When low, TG and BG are forced low and the supply current (5V) is less than 10A. +5V supply. A .22-1F ceramic capacitor should be connected from 5V to PGND very close to this pin. Output drive for the synchronous (bottom) MOSFET. Ground.
NOTE: (1) All logic level inputs and outputs are open collector TTL compatible.
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SC1205
POWER MANAGEMENT Block Diagram
Applications Information
SC1205 is a high speed, smart dual MOSFET driver. It is designed to drive Low Rds_On power MOSFET's with ultra-low rise/fall times and propagation delays. As the switching frequencies of PWM controllers is increased to reduce power supply volume and cost, fast rise and fall times are necessary to minimize switching losses (TOP MOSFET) and reduce Dead-time (BOTTOM MOSFET). While Low Rds_On MOSFET's present a power saving in I2R losses, the MOSFET's die area is larger and thus the effective input gate capacitance of the MOSFET is increased. Often a 50% decrease in Rds_On more than doubles the effective input gate charge, which must be supplied by the driver. The Rds_On power savings can be offset by the switching and dead-time losses with a sub_optimum driver. While discrete solutions can achieve reasonable drive capability, implementing shoot-through and other housekeeping functions necessary for safe operation can become cumbersome and costly. The SC120X family of parts presents a total solution for the high-speed high power density applications. Wide input supply range of 4.5V-25V allows use in battery powered applications, new high voltage, distributed power servers as well as Class-D amplifiers. THEORY OF OPERATION The control input (CO) to the SC1205 is typically supplied by a PWM controller that regulates the power supply output. (See Application Evaluation Schematic, Figure 4). The timing diagram demonstrates the sequence of events
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by which the top and bottom drive signals are applied. The shoot-through protection is implemented by holding the bottom FET off until the voltage at the phase node (intersection of top FET source, the output inductor and the bottom FET drain) has dropped below 1V. This assures that the top FET has turned off and that a direct current path does not exist between the input supply and ground. The top FET Gate Drive is turned on after the bottom gate drive has gone low and an internal delay time of 20ns has expired. LAYOUT GUIDELINES As with any high speed , high current circuit, proper layout is critical in achieving optimum performance of the SC1205. The Evaluation board schematic (Refer to figure 3) shows a two-phase synchronous design with all surface mountable components. While components connecting to EN are relatively noncritical, tight placement and short, wide traces must be used in layout of The gate drives, DRN, and especially PGND pin. The top gate driver supply voltage is provided by bootstrapping the +5V supply and adding it to the phase node (DRN) voltage . Since the bootstrap capacitor supplies the charge to the top gate, it must be less than .5" away from the SC1205. Ceramic X7R capacitors are a good choice for supply bypassing near the chip. The Vcc pin capacitor must also be less than .5" away from the SC1205. The ground node of this capacitor,
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SC1205
POWER MANAGEMENT Applications Information (Cont.)
the SC1205 PGND pin and the Source of the bottom FET must be very close to each other, preferably with common PCB copper land with multiple vias to the ground plane (if used). The parallel Schottky (if used) must be physically next to the Bottom FET's drain and source pins. Any trace or lead inductance in these connections will drive current way from the Schottky and allow it to flow through the FET's Body diode, thus reducing efficiency. Preventing Inadvertent Bottom FET Turn-on At high input voltages, (12V and greater) a fast turn-on of the top FET creates a positive going spike on the Bottom FET's gate through the Miller capacitance, Crss of the bottom FET. The voltage appearing on the gate due to this spike is:
V SPIKE = Vin * crss ( Crss + ciss
does this at the expense of increased switching times (and switching losses) for the top FET. RINGING ON THE PHASE NODE The top MOSFET source must be close to the bottom MOSFET drain to prevent ringing and the possibility of the phase node going negative. This frequency is determined by:
Fring = 1 ( 2 * Sqrt (L ST * Coss )
Where: Lst = The effective stray inductance of the top FET added to trace inductance of the connection between top FET's source and the bottom FET's drain added to the trace resistance of the bottom FET's ground connection. Coss=Drain to source capacitance of bottom FET. If there is a Schottky used, the capacitance of the Schottky is added to this value. Although this ringing does not pose any power losses due to a fairly high Q, it could cause the phase node to go too far negative, thus causing improper operation, double pulsing or at worst driver damage. On the SC1205, the drain node, DRN, can go as far as 2V below ground without affecting operation or sustaining damage. The ringing is also an EMI nuisance due to its high resonant frequency. Adding a capacitor, typically 10002000pf, in parallel with Coss of the bottom FET can often eliminate the EMI issue. If double pulsing, due to excessive ringing, placing a 4.7-10 ohm resistor between the phase node and the DRN pin of the SC1205 should eliminate the double pulsing. The negative voltage spikes on the phase node adds to the bootstrap capacitor voltage, thus increasing the voltage between VBST - VDRN. If the phase node negative spikes are too large, the voltage on the boost capacitor could exceed device's absolute maximum rating of 7V. To eliminate the effect of the ringing on the boost capacitor voltage, place a 4.7 - 10 Ohm resistor between boost Schottky diode and Vcc to filter the negative spikes on DRN Pin. Alternately, a Silicon diode, such as the commonly available 1N4148 can substitute for the Schottky diode and eliminate the need for the series resistor.
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Where Ciss is the input gate capacitance of the bottom FET. This is assuming that the impedance of the drive path is too high compared to the instantaneous impedance of the capacitors. (since dV/dT and thus the effective frequency is very high). If the BG pin of the SC1205 is very close to the bottom FET, Vspike will be reduced depending on trace inductance, rate of rise of current, etc. While not shown in Figure 4, a capacitor may be added from the gate of the Bottom FET to its source, preferably less than .5" away. This capacitor will be added to Ciss in the above equation to reduce the effective spike voltage. The bottom MOSFET must be selected with attention paid to the Crss/Ciss ratio. A low ratio reduces the Miller feedback and thus reduces Vspike. Also MOSFETs with higher Turn-on threshold voltages will conduct at a higher voltage and will not turn on during the spike. The MOSFET shown in the schematic (Figure 4) has a 2 volt threshold and will require approximately 4.5 volts Vgs to be conducting, thus reducing the possibility of shoot-through. A zero ohm bottom FET gate resistor will obviously help keeping the gate voltage low during off time. Ultimately, slowing down the top FET by adding gate resistance will reduce di/dt which will in turn make the effective impedance of the capacitors higher, thus allowing the BG driver to hold the bottom gate voltage low. It
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SC1205
POWER MANAGEMENT Applications Information (Cont.)
Proper layout will guarantee minimum ringing and eliminate the need for external components. Use of SO-8 or other surface mount MOSFETs while increasing thermal resistance, will reduce lead inductance as well as radiated EMI. Over Temp Shutdown The SC1205 will shutdown by pulling both driver if its junction temperature, TJ, exceeds 165 C.
Typical Performance Plots
Figure 1: PWM input and Gate drive switching waveforms. The MOSFETs driven are FDB7030BL . See Figure 4 (Evaluation Board Schematic) Ch1: PWM input signal Ch2: Top Gate Drive Ch3: Phase (Switching) Node Ch4: Bottom Gate
Figure 2: PWM input and Gate drive and phase node switching waveforms with time scale expanded. The MOSFETs driven are FDB7030BL . See Figure 4 (Evaluation Board Schematic) Ch1: PWM input signal Ch2: Top Gate Drive Ch3: Phase (Switching) Node Ch4: Bottom Gate
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SC1205
POWER MANAGEMENT Typical Performance Plots
Figure 3: PWM input and Gate drive and phase node switching waveforms with time scale expanded. The MOSFETs driven are FDB7030BL . See Figure 4 (Evaluation Board Schematic) Ch1: PWM input signal Ch2: Top Gate Drive Ch3: Phase (Switching) Node Ch4: Bottom Gate
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1u,16V
820uf,16V
820uf,16V
820uf,16V
3
BST
X
POWER MANAGEMENT Evaluation Board Schematic - 3SC1205
CO SC1205S 8
GND
R32 24.3K R20 10k 6 VS EN U3 10 R33 9 10.0K
3
BST
R19 26.7k 11.5k
CO 1uf SC1205S C26
GND
local gnd
R17 6.49k
8
*
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+5V 1uf C1 10u,CER C4 10u,CER C2 1uf C3 R3 10u,CER 22nf 10 ^ 1uf 4.7-10 ohm LL42 U1 Q1 TG 1 FDB7030BL EN BG 4 13 7 R8 0 Q3 10u,CER C17 10u,CER C19 .1 LL42 FDB7030BL TG DRN 2 1 FDB7030BL R9 0 Q4 C22 TTIB1106-708 L2 L1 2 R5 0 FDB7030BL 820uf,16V C14 .1 C15 TTIB1106-708 C13 S1 U2 D7 C11 R30 133 R31 100 VCC 1uf C18 6 VS DRN 5 BGOUT OC+ OUT1 14 15 16 820uf,16V C12 C6 R2 10 R1 .005 VIN
Vin
820uf,OS C33 820uf,16V C5
Figure 4- Microprocessor Core Supply
J1
1 2 3 4 5 C9 6 C7 C10 C34
INPUT
EN
1 VID4 VID3 VID2 VID1
* +5V EN
ENABLE 2 3 4
820uf,16V C35 10u,CER C16
9 10 11 12 13 14 15 16 Vout/Clk swit ch
8 7 6 5 4 3 2 1
*
^ D6 4.7-10 ohm
5 VID0 ERROUT FB RREF GND UVLO OC11 OUT2 6 7 R10 100K 100pf C25 R14 SC2422A C21 .1 4 10k 8 R11
12
R99 0
10
EN5
BG R18 1
10u,CER C20 10u,CER C23
1.7V
7
10u,CER C24 R13 0 Q5 10u,CER C28 10u,CER C29 10u,CER C31
Cut at X and install R99 to enable Driver side UVLO
VCORE
^ Install resistor to limit voltage rise on boost capacitor due to large phase node negative spikes.
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SC1205
SC1205
POWER MANAGEMENT Evaluation Board Bill of Materials
Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Qty 5 12 7 1 1 3 1 1 2 1 2 4 1 2 5 1 2 1 1 1 1 1 1 1 1 1 2 1 1 Reference C1,C4,C13,C18,C26 C2,C3,C6,C16,C17,C19,C20, C23,C24,C28,C29,C31 C5,C7,C10,C12,C14,C34, C35 C9 C11 C 15, C 21, C 22 C 25 C 33 D 7, D 6 J1 L2, L1 Q1, Q3, Q4, Q5 R1 R2, R3 R5,R8,R9,R13,R99 R10 R11, R20 R14 R17 R18 R19 R30 R31 R32 R33 S1 U3, U1 U2 optional S C 1205 S C 2422A 4.7-10 ohm Semtech Semtech TTIB1106-708, 700nh F D B 7030B L .005 10 0 100K 10k 11.5k 6.49k 1 26.7k 133 100 24.3K 10.0K FALCO Fairchild Dale Part Number/Value Manufacturer 1uf 10u,CER 820uf,16V 1u, 16V 22nf .1 100pf 820uf, OS LL42 Sanyo Panasonic
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SC1205
POWER MANAGEMENT Outline Drawing - SO-8
A N 2X E/2 E1 E 1 ccc C 2X N/2 TIPS 2 e/2 B D aaa C SEATING PLANE A2 A C bxN bbb A1 C A-B D GAGE PLANE 0.25 SEE DETAIL SIDE VIEW L (L1) DETAIL e D
DIM
A A1 A2 b c D E1 E e h L L1 N 01 aaa bbb ccc
DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX
.053 .069 .004 .010 .049 .065 .012 .020 .007 .010 .189 .193 .197 .150 .154 .157 .236 BSC .050 BSC .010 .020 .016 .028 .041 (.041) 8 0 8 .004 .010 .008 1.35 1.75 0.10 0.25 1.25 1.65 0.31 0.51 0.17 0.25 4.80 4.90 5.00 3.80 3.90 4.00 6.00 BSC 1.27 BSC 0.25 0.50 0.40 0.72 1.04 (1.04) 8 0 8 0.10 0.25 0.20
h h
H
c
01
A
A
NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MS-012, VARIATION AA.
Land Pattern - SO-8
X
DIM
(C) G Z C G P X Y Z
DIMENSIONS INCHES MILLIMETERS
(.205) .118 .050 .024 .087 .291 (5.20) 3.00 1.27 0.60 2.20 7.40
Y P
NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET.
2. REFERENCE IPC-SM-782A, RLP NO. 300A.
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804
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